1. Field of the Invention
The present invention relates to field effect transistors and, more particularly, to a field effect transistor used in a Static Random Access Memory (hereinafter referred to as "SRAM") and a manufacturing method thereof.
2. Description of the Background Art
A SRAM is a RAM in which information is stored as long as voltage is supplied. Compared to a DRAM (Dynamic Random Access Memory), the SRAM does not need a refresh circuit and is excellent at a high speed operation. FIG. 36 is a schematic diagram of an equivalent circuit of the SRAM. An inverter 1 and an inverter 3 constitute a flipflop circuit. An access transistor 5 has one of source and drain connected to the flipflop circuit at a connection portion B, and the other of source and drain connected to a BL. An access transistor 7 has one of source and drain connected to the flipflop circuit at a connection portion A, and the other of source and drain connected to a /BL. A memory cell is formed of inverters 1, 3 and access transistors 5, 7. A WL is connected to the gates of access transistors 5, 7.
Writing operation for storing a state of "H" will be described. First, BL is set in an "H" state, and/BL is set in an "L" state. A voltage is applied to WL, so that access transistors 5, 7 are turned on. Since BL is in an "H" state, connection portion B is also in an "H" state. Also, since /BL is in an "L" state, connection portion A is in an "L" state. The voltage applied to WL is then removed so that access transistors 5, 7 are turned off. Connection portion B is in an "H" state and therefore connection portion A is brought into an "L" state through inverter 3. Also, connection portion A is in an "L" state and therefore connection portion B is brought into an "H" state through inverter 1. Thus, connection portion B is held in an "H" state, and connection portion A is held in an "L" state.
Next, reading operation will be described. A voltage is applied to WL so that access transistors 5, 7 are turned on. Since connection portion B is in an "H" state, BL is brought into an "H" state. Since connection portion A is in an "L" state, /BL is brought into an "L" state. However, the difference between the voltage of an "H" state and the voltage of an "L" state is not so large. A sense amplifier compares the voltage of BL and the voltage of /BL in order that determination is made without fail that BL is in an "H" state. As a result, determination is made that the voltage of BL is larger than the voltage of /BL. Since the voltage of BL is larger than the voltage of /BL, BL should be in an "H" state. Therefore, it can be seen that "H" is stored in this memory circuit.
The inverters will be described. FIG. 37 is a schematic diagram of an equivalent circuit of inverter 1. 9 denotes a PMOS transistor and 11 an NMOS transistor. When V.sub.in is in an "H" state, PMOS transistor 9 is held off, NMOS transistor 11 is held on, and V.sub.out is in an "L" state. Conversely, when V.sub.in is in an "L" state, PMOS transistor 9 is held on, NMOS transistor 11 is held off, and V.sub.out is in an "H" state.
FIG. 38 is a schematic diagram of an equivalent circuit when an output of inverter 1 is connected to an input of inverter 3 and an input of inverter 1 is connected to an output of inverter 3. The circuit forms a flipflop circuit. Inverter 3 includes a PMOS transistor 13 and an NMOS transistor 15. 25 denotes a gate electrode of PMOS transistor 13. 21 denotes a gate electrode of access transistor 7. 17 denotes a gate electrode of NMOS transistor 11.
As can be seen from FIG. 38, a memory cell of the SRAM comprises two PMOS transistors and four NMOS transistors. If all these transistors are formed on the same plane, that is, the main surface of a silicon substrate, an integration density decreases. Therefore, the PMOS transistors are located above the NMOS transistors.
FIG. 39 is a sectional view of a memory cell of the SRAM. The same reference characters as those in FIG. 38 denote the same portions. Access transistor 7 and NMOS transistor 11 are formed on a main surface 24 of a silicon substrate 22. Access transistor 7 includes a gate electrode 21 and source/drain regions 19, 23 in silicon substrate 22 with a space therebetween. 17 denotes a gate electrode of NMOS transistor 11. A source/drain of NMOS transistor 11 is not shown in this figure. 35 denotes a field oxide film.
An interlayer insulating film 33 is formed on gate electrode 17. A gate electrode 25 is formed on interlayer insulating film 33. A polycrystalline silicon film 31 is formed to cover gate electrode 25. A portion of polycrystalline silicon film 31 facing gate electrode 25 is a channel region 28. A channel region 28 is interposed between source/drain regions 27, 29 in polycrystalline silicon film 31. Polycrystalline silicon film 31 and gate electrode 17 are electrically connected to a source/drain region 19.
FIG. 40 is a plan view of PMOS transistor 13 shown in FIG. 39. 25 denotes the gate electrode, and 27, 29 denote source/drain regions. A method of manufacturing PMOS transistor 13 shown in FIG. 39 will be described. The same reference characters as those in FIG. 38 denote the same portions. As shown in FIG. 41, a polycrystalline silicon film is formed on interlayer insulating film 33 using a low pressure CVD (Chemical Vapor Deposition) method. The polycrystalline silicon film is patterned to form gate electrode 25 using photolithography and etching.
As shown in FIG. 43, a gate insulating film 37 is formed on gate electrode 25 using the low pressure CVD method. A polycrystalline silicon film 31 is formed on gate insulating film 37 using the low pressure CVD method.
As shown in FIG. 43, a resist 39 is formed on polycrystalline silicon film 31. Resist 39 is subjected to predetermined patterning. BF.sub.2 is implanted into polycrystalline silicon film 31 using resist 39 as a mask.
As shown in FIG. 44, resist 39 is removed. Boron of BF.sub.2 is properly diffused in polycrystalline silicon film 31 through heat treatment, so that source/drain regions 27, 29 are formed. 28 denotes the channel region.
L.sub.1 +L.sub.2 +L.sub.3 is a channel length. Channel lengths tend to become shorter as integration density of an SRAM increases. If a channel length is short, a short channel effect which causes deterioration of characteristics of a field effect transistor is produced.
A field effect transistor shown in FIG. 45 was devised in order to solve the problem. The field effect transistor is disclosed in "A 0.5 .mu.m BiCMOS Technology for Logic and 4M bit-class SRAM's", pp. 425-428, IDEM 89.
A gate electrode 47 of a transistor 44 is embedded in trench 41 formed in a semiconductor substrate 40 and an epitaxial layer 42. A source/drain region 43 is formed in epitaxial layer 42. Source/drain region 45 which is an N.sup.+ embedded layer is formed in silicon substrate 40. Field effect transistor 44 has a channel region formed in the depth direction of trench 41. L indicates a channel length. Gate length L can be sufficient to prevent a short channel effect in field effect transistor 44 if the thickness of epitaxial layer 42 is increased.
Transistor 44 shown in FIG. 45 is manufactured by forming source/drain region 45 in semiconductor substrate 40, subsequently forming epitaxial layer 42 on semiconductor substrate 40, and forming trench 41 in epitaxial layer 42.
Forming an epitaxial layer takes time, and time required for manufacturing transistor 44 increases.